Aion Silicon (formerly Sondrel), a premier ASIC/SoC architecture and design partner, today announced the release of its white paper “Considerations When Architecting Your Next SoC: NoC.” The paper provides a practical framework when making network-on-chip (NoC) decisions for AI SoCs.
The white paper explores how AI workloads are fundamentally changing semiconductor design priorities. As compute density increases in AI applications, the NoC has evolved from a connectivity layer to a primary determinant of power efficiency, schedule risk, and overall system throughput.
“Modern AI SoCs are forcing architects to treat the NoC as a first-order design decision rather than a late-stage interconnect choice,” said Oliver Jones, CEO of Aion Silicon. “It is no longer enough to focus solely on compute density. Today, the bottleneck is movement. This white paper distills our experience helping customers navigate these architectural decisions early enough to avoid schedule-threatening surprises and deliver silicon that performs under real-world conditions.”
Key White Paper Insights:
- Shift in NoC Priority: Why AI workloads require a move away from traditional bus architectures toward sophisticated NoCs that handle bursty traffic and high concurrency
- Coherency Paradigms: A deep dive into the trade-offs between hardware-based (HwCC) and software-managed (SwMM) coherency for AI accelerators
- Bridging Architecture and Physical Reality: Strategies for aligning NoC topology with floorplan constraints early in the design cycle to prevent timing and congestion failures
- Performance Tuning: The role of specialized hardware units, such as reorder buffers and QoS arbiters, in maintaining system throughput
- Proven Methodology: A five-step sequencing guide to reduce risk, from traffic modeling to RTL validation
Considerations When Architecting Your Next SoC: NoC is based on the SemiWiki live webinar of the same name featuring Piyush Singh, Aion Silicon and Andy Nightingale,VP Product Management & Marketing at Arteris.
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