Aion Silicon (formerly Sondrel), a premier ASIC/SoC architecture and design partner, today announced its white paper “Architecting the Future: Building Smarter SoCs with RISC-V,” a practical guide for semiconductor teams balancing performance, flexibility, and commercial risk from concept to silicon.
As advanced-node costs climb and AI-driven workloads grow more complex, architecture decisions are carrying unprecedented financial weight. The new white paper outlines how structured modeling, disciplined trade-offs, and early ecosystem alignment can reduce re-spins and protect market windows.
Based on a joint SemiWiki webinar with Andes Technology, the paper examines how RISC-V’s open, modular instruction set architecture can be leveraged intentionally, rather than impulsively, to deliver measurable gains in performance and power efficiency without introducing schedule risk.
“On advanced nodes, the cost of getting the architecture wrong is now on the same order as the cost of the chip itself,” said Paul Martin, Global Director of SoC Architecture at Aion Silicon. “Architecture is the only phase where you can still change fundamental compute structures and memory hierarchies without rewriting the entire design. This paper serves as a roadmap for turning that vision into predictable execution.”
Key White Paper Insights:
- The Discipline of Customization: How to use RISC-V’s modularity intentionally rather than impulsively, tying every custom instruction to measurable KPI gains
- Data-Driven Trade-offs: A framework for evaluating the “ripple effects” of cache size, interconnect topology, and processor selection on Power, Performance, and Area (PPA)
- Cycle-Based Modeling: Utilizing SystemC-based simulation to prove design viability and identify contention bottlenecks before a single line of RTL is written
- Ecosystem Alignment: Why technical specifications alone fail without proactive coordination between IP suppliers, EDA vendors, and foundries
- Specialized AI Workloads: Strategies for modeling Deep Neural Network (DNN) graphs to optimize memory efficiency and throughput
“RISC-V changes the game by allowing teams to shape compute architecture precisely to the workload,” said Darren Jones, Distinguished Engineer at Andes Technology. “However, that freedom requires early, joint planning to ensure that architectural tweaks are validated through modeling to avoid the late-stage support issues that typically cause schedule slips.”
Architecting the Future: Building Smarter SoCs with RISC-V is based on the SemiWiki live webinar of the same name featuring Paul Martin, Global Director of SoC Architecture at Aion Silicon, and Darren Jones, Distinguished Engineer and Solutions Architect at Andes Technology.
About Aion Silicon
Aion Silicon is a trusted partner in high-performance semiconductor design, specializing in advanced System-on-Chip (SoC) solutions – including tailored ASICs – for AI, automotive, HPC, 5G, networking, and other applications. Its full-service, high-touch engineering model with consultative project leadership guides customers from SoC architecture and IP selection through design, foundry tapeout, and volume production. With over 20 years of experience in SoC architecture, front-end and back-end services, Aion Silicon reduces technical and economic risk for customers, accelerating time-to-market, while optimizing for commercial success. As a foundry-neutral and IP-agnostic partner with hundreds of successful tapeouts, Aion Silicon leverages a world-class ecosystem to deliver tailored solutions that meet each customer’s unique needs. To learn more, visit www.aionsilicon.com.
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